Exemplary embodiments of the present invention relate to a semiconductor device and a method of manufacturing the same and, more particularly, to a 3D non-volatile memory device and a method of manufacturing the same.
A non-volatile memory device is a memory device in which data stored therein is maintained as it is although power supply applied thereto is cut off. As the enhancement of the degree of integration of a memory device having a two-dimensional (2D) structure in which memory cells are formed as a single layer on a silicon substrate has reached the limit, a three-dimensional (3D) non-volatile memory device in which a plurality of memory cells are stacked vertically on a silicon substrate has been proposed.
Hereinafter, a structure and features of the conventional 3D non-volatile memory device and will be described in detail with reference to the accompanying drawings.
FIG. 1 is a perspective view illustrating a structure of the conventional 3D non-volatile memory device. Here, interlayer insulating layers are omitted for the description purposes.
As illustrated in FIG. 1, the conventional 3D non-volatile memory device includes a channel CH including a pipe channel layer P_CH formed in a pipe gate PG and a pair of source side channel layer S_CH and a drain side channel layer D_CH connected to the pipe channel layer P_CH.
Also, the memory device includes source side word lines S_WL surrounding the source side channel layer S_CH and drain side word lines D_WL surrounding the drain side channel layer D_CH. Here, the source side word lines S_WL and the drain side word lines D_WL extend in a first direction I-I′, and they are arranged in parallel with each other. Also, at least one source selection line SSL is formed over the source side word lines, and at least one drain selection line DSL is formed over the drain side word lines D_WL.
Here, the source side channel layers S_CH of strings ST0 and S1 neighboring in a second direction II-II′ are commonly connected to a single source line SL, and the drain side channel layers D_CH of the strings ST0 and S1 extending in the second direction II-II′ are commonly connected to a single bit line BL.
However, according to the foregoing structure, since the narrow word lines S_WL and D_WL are stacked high, the word line stacked structure may incline (or tilt). Also, in manufacturing a memory device, by etching stacked interlayer insulating layers and conductive layers, slits are to be formed every between a pair of source side channel layer S_CH and drain side channel layer D_CH constituting a single channel and every between neighboring channels CH. The slits have a narrow width and the etching process has a high degree of difficulty in the foregoing structure of the memory device. In addition, as the degree of integration of a memory device is increased, the number of stacked word lines is further increased accordingly, aggravating the features of the memory device.